1. Field of the Invention
The present invention relates generally to liquid crystal display devices and, more particularly, is directed to a liquid crystal display device in which liquid crystal display elements are arranged in an X-Y matrix form to display a visual image.
2. Description of the Prior Art
Japanese Patent Laid-Open Gazette No. 59-220793 describes, for example, a liquid crystal display device which utilizes a liquid crystal to display a television picture. FIG. 1 shows an example of such prior-art liquid crystal display device.
Referring to FIG. 1, a television video signal is supplied to an input terminal 1, and the signal applied to the input terminal 1 is supplied through switching elements M.sub.1, M.sub.2, . . . , M.sub.m, each being formed, for example, of an N-channel field effect transistor (FET), to lines L.sub.1, L.sub.2, . . . , L.sub.m in the vertical direction (Y-axis direction) where m represents the number corresponding to the number of pixels (picture elements) in the horizontal (X-axis) direction.
There is provided a shift register 2 having m stages, and the shift register 2 is supplied with clock signals .PHI..sub.1H and .PHI..sub.2H having a frequency of m times as high as the horizontal frequency. Drive pulse signals .phi..sub.H1, .phi..sub.H2, . . . , .phi..sub.Hm, sequentially scanned by the clock signals .PHI..sub.1H and .PHI..sub.2H are supplied to control terminals of the switching elements M.sub.1 to M.sub.m from the output terminals of the shift register 2. The shift register 2 is supplied with a low potential (low voltage) V.sub.SS and a high potential (high voltage) V.sub.DD, and generates the drive pulse signal which goes to a high level or low level.
The lines L.sub.1 to L.sub.m are connected with one ends of switching elements M.sub.11, M.sub.21, . . . , M.sub.n1, M.sub.12, M.sub.22, . . . , M.sub.n2, . . . M.sub.1m, M.sub.2m, . . . , M.sub.nm, each being formed, for example, of an N-channel field effect transistor (FET) where n represents the number corresponding to the number of horizontal scanning lines. The other ends of the switching elements M.sub.11 to M.sub.nm are connected through liquid crystal cells C.sub.11, C.sub.21, . . . , C.sub.nm to a target terminal 3.
Further, there is provided a shift register 4 of n stages. This shift register 4 is supplied with clock signals .PHI..sub.1V and .PHI..sub.2V having a horizontal frequency. Drive pulse signals .phi..sub.V1, .phi..sub.V2, . . . , .phi..sub.Vn, sequentially scanned by the clock signals .PHI..sub.1V and .PHI..sub.2V, are respectively supplied through gate lines G.sub.1, G.sub.2, . . . , G.sub.n, aligned in the horizontal (X-axis) direction, to control terminals of the switching elements M.sub.11 to M.sub.1m, M.sub.21 to M.sub.2m, . . . , M.sub.n1 to M.sub.nm aligned in the X-axis direction of the switching elements M.sub.11 to M.sub.nm from the output terminals of the shift register 4. The shift register 4 is supplied with the low and high voltages V.sub.SS and V.sub.DD, similarly to the shift register 2.
In the aforementioned circuit arrangement, the shift registers 2 and 4 are supplied with the clock signals .PHI..sub.1H, .PHI..sub.2H, and .PHI..sub.1V, .PHI..sub.2V shown in FIGS. 2A and 2B, whereby the shift register 2 derives the drive pulse signals .phi..sub.H1 to .phi..sub.Hm, shown in FIG. 2C, at every pixel period, and the shift register 4 derives the drive pulse signals .phi..sub.V1 to .phi..sub.Vn, shown in FIG. 2D, at every horizontal period. A video signal shown in FIG. 2E is supplied to the input terminal 1.
When the drive pulse signals .phi..sub.V1 and .phi..sub.H1 are produced from the shift registers 4 and 2, the switching element M.sub.1 and the switching elements M.sub.11 to M.sub.1m are turned ON to form a current path formed of the input terminal 1, the switching element M.sub.1, the line L.sub.1, the switching element M.sub.11, the liquid crystal cell C.sub.11 and the target terminal 3, in that order, whereby a potential difference between the signal applied to the input terminal 1 and the signal at the target terminal 3 is supplied to the liquid crystal cell C.sub.11. Accordingly, a charge corresponding to the potential difference, brought about by a signal of a first pixel, is sample-and-held in the capacity of the liquid crystal cell C.sub.11, and an optical transmissivity of the liquid crystal cell is changed in response to the amount of charges. The liquid crystal cells C.sub.12 to C.sub.nm are similarly driven in that order, and the amounts of charge in the liquid crystal cells C.sub.11 to C.sub.nm are rewritten when a signal of the next field is supplied to the input terminal 1.
In this fashion, optical transmissivities of the liquid crystal cells C.sub.11 to C.sub.nm are varied in response to the respective pixels of the video signal, and this operation is sequentially repeated to display a television picture.
In general, the liquid crystal display device is driven to display a picture by an AC voltage in order to increase a reliability thereof and a life thereof. For example, when a television picture is displayed, a signal in which a video signal is inverted at every field or at every frame is supplied to the input terminal 1. Further, in the liquid crystal display device, a signal is inverted at every horizontal period in order to avoid a so-called shooting in the vertical direction of a displayed image and so on.
More specifically, the input terminal 1 is supplied with a video signal which is inverted at every horizontal period and which is inverted at every field or at every frame as shown in FIG. 2E.
In the above-described liquid crystal display device, a duration of each of the drive pulse signals .phi..sub.H1 to .phi..sub.Hm derived from the shift register 2 is determined as ##EQU1## For example, in the case of the NTSC video signal, a duration of a drive pulse signal is about 100 nanoseconds. When the above-described liquid crystal display device is applied to a high definition television receiver (HDTV), a time of a horizontal effective picture screen period becomes about one-half and the number of horizontal pixels is increased by about three times, whereby the duration of the above-mentioned drive pulse signal is reduced to about one-sixth.
Thus, the video signals, passing through the switching elements M.sub.1 to M.sub.m during the period of the drive pulse signals .phi..sub.H1 to .phi..sub.Hm, are supplied through the lines L.sub.1 to L.sub.m to the switching elements M.sub.11 to M.sub.nm. In that case, a wiring capacity of 10 to several 10s of picofarads exists in each of the lines L.sub.1 to L.sub.m so that the video signal charges this capacity and is then supplied to the switching elements M.sub.11 to M.sub.nm.
In that case, if a period in which the video signal is supplied is about 100 nanoseconds, the above-mentioned charged voltage is increased to a signal potential. If the charging time is reduced to one-sixth, when the video signal is at a high potential (white or black), the charging is not carried out satisfactorily so that only an unclear picture having insufficient contrast or the like is displayed. In the case of the HDTV system, the wiring capacity is increased more.
In order to avoid the above-mentioned defects, U.S. Pat. No. 4,447,812 describes the following proposal. In this proposal, an input video signal is converted to parallel signals of three pixels each by using delay means whose delay time corresponds, for example, to a period of one to two pixels. The resultant parallel signals are supplied through three of the switching elements M.sub.1 to M.sub.m to the lines L.sub.1 to L.sub.m, and the three switching elements are driven by a common drive pulse signal, whereby a duration of a pulse signal can be increased, for example, by about three times.
In this proposal, the characteristics of delay means for providing the parallel signals or the like must be made uniform at very high accuracy, otherwise a fixed pattern of low frequency appears in the displayed image and the image quality is considerably deteriorated. In the liquid crystal display device, the shift register 2 can be driven at very high speed when the liquid crystal display device is applied to the HDTV system.